The present invention relates to a semiconductor design technology, and more particularly, to a multi-port memory device for detecting a defect of a memory cell.
Recently, the application range for a dynamic random access memory (DRAM) has been expanded from conventional devices such as desktop computers, laptop computers and servers to audio/video devices such as high definition television (HDTV). Accordingly, it is required that conventional way of data input/output of the DRAM be modified to a new way of data input/output. Herein, the conventional way of data input/output means a parallel input/output interface where a data exchange is performed through a single port which includes a plurality of input/output pins.
FIG. 1 is a block diagram showing a conventional single-port memory device. In this particular example, the conventional single-port memory device is an x16, 512M DRAM which includes 8 banks.
The conventional single-port memory device includes first to an eighth banks BANK0 to BANK7, a port (PORT), and a plurality of communication lines (GIO).
Each of the first to the eighth banks BANK0 to BANK7 includes an n×m number of memory cells arranged in a matrix form. The port performs individual communication with the first to the eighth banks BANK0 to BANK7. The plurality of communication lines provides for a signal transfer between the port and a pin, and between the port and first to the eighth banks BANK0 to BANK7.
Herein, the communication lines are global I/O lines generally included in the DRAM including a control bus, 15 lines of address bus and 16 lines of information bus.
With conventional single-port memory devices, since a single-port is used, it is difficult to embody various multimedia functions. For embodying such multimedia functions using single-port memory devices, plural numbers of memory devices, e.g., DRAMs, should be independently constituted so that each DRAM performs a different function. However, in case of independently operating DRAMs, it is difficult to appropriately allocate memory among a plurality of devices which have different amounts of memory access. Therefore, memory usage efficiency is decreased compared with using a single memory device.
For solving the above-mentioned problem, the applicant of the present invention proposed a multi-port memory device having a serial input/output interface as disclosed in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”.
FIG. 2 is a block diagram showing a conventional multi-port memory device.
In the illustrated example, the multi-port memory device includes 4 ports, i.e., PORT0 to PORT3, 8 banks, i.e., BANK0 to BANK7, has a 16-bit data frame, and performs a 64-bit prefetch operation.
Referring to FIG. 2, the multi-port memory device includes a first to a fourth ports PORT0 to PORT3 for independently performing a serial communication with different external devices; first to eighth banks BANK0 to BANK7 located in rows at an upper part and a lower part from the first to the fourth ports PORT0 to PORT 3 (upper part: BANK0 to BANK3, lower part: BANK4 to BANK7); global output lines GIO_OUT located in a row between the first to the fourth ports PORT0 to PORT3 and the first to the fourth banks BANK0 to BANK3 for performing parallel information transfer; global input lines GIO_IN arranged in a row between the first to the fourth ports PORT0 to PORT3 and the fifth to the eighth banks BANK4 to BANK7 for performing parallel information transfer; first to an eighth bank control units BCL0 to BCL7 for controlling data and a signal transfers between the global input/output lines and first to the eighth banks BANK0 to BANK7; and a PLL unit located between the second port PORT1 and the third port PORT2 for clocking internal commands and data input to first to fourth ports PORT0 to PORT3.
The multi-port memory device includes a plurality of ports, and independent operations can be performed at each port. Therefore, the multi-port memory device can be used as a memory of a digital device which requires high speed data processing.
Further, through data received from the first to the fourth ports PORT0 to PORT3, an address and an internal command are generated. For distinguishing the address and the internal command from data, a predetermined protocol (data frame) is generally used.
FIGS. 3A to 3F are diagrams depicting a data frame of the multi-port memory device.
In detail, FIG. 3A depicts a basic frame; FIG. 3B depicts a write command frame; FIG. 3C depicts a write data frame; FIG. 3D depicts a read command frame; FIG. 3E depicts a read data frame; and FIG. 3F depicts a command frame.
Referring to FIG. 3B, the 19th and the 18th bits are physical link coding (PHY) bits which are not substantially used; the 17th bit is a command (CMD) bit; and the 16th to the 14th bits are active command (ACT), write command (WT) and precharge command (PCG) bits respectively. For input of a normal write command, the 17th to 15th bits and the 14th bits should be ‘1’, ‘0’, ‘1’ and ‘0’ respectively; and for input of a precharge command and write command, the 17th to 15th bits and the 14th bits should be ‘1’, ‘0’, ‘1’ and ‘1’ respectively.
Meanwhile, the 13th to the 10th bits are upper byte write data mask (UDM) for controlling a transfer of an upper byte of the write data frame; the 9th to 6th bits are bank information (BANK) to be written; and the 5th the 0th bits represent a column address.
Next, referring to FIG. 3C, the 19th and the 18th bits are physical link coding (PHY) bits which are not substantially used; the 17th bit is a command (CMD) bit; a 16th bit is a lower byte write data mask (LDM) for controlling a transfer of a lower byte of the write data; the 15th the 8th bits are the upper byte of the write data; and the 7th to the 0th bits are the lower byte of the write data. For an input of a normal write data, the 17th bit, i.e., the CMD bit, should be ‘0’.
Next, referring to the frame FIG. 3D, the 19th and the 18th bits are physical link coding (PHY) bits which are not substantially used; the 17th bit is a command (CMD) bit; the 16th to the 13th bits are active command (ACT), write command (WT), precharge command (PCG) and read command (RD) bits respectively.
For input of a normal read command, the 17th to the 13th bits should be ‘1’, ‘0’, ‘0’, ‘0’ and ‘1’ respectively; and for a write operation accompanied with a precharge operation, the 17th to the 13th bits should be ‘1’, ‘0’, ‘0’, ‘1’ and ‘1’ respectively.
Meanwhile, the 12th bit is a command extension (ESC(escape)) bit. For instance, when the command bit is ‘1’ and the precharge command bit is ‘1’ and the read command bit is ‘1’ for an all-banks precharge operation, the command extension bit serves to input a command of the all-banks precharge operation. That is, since there is no bit for representing the all-banks precharge operation, the all-banks precharge operation and an auto refresh operation are performed by using the command extension bit and the existing command bits.
Further, the 11th bit is a bank activation (ABNK(active bank)) bit which is set during setting of the read command bit; the 9th to the 6th bits are bank information (BANK) to be written; and the 5th to the 0th bits represent a column address.
Next, referring to FIG. 3E, the 19th and the 18th bits are physical link coding (PHY) bits which are not substantially used; the 15th to the 8th bits are upper byte of a read data; and the 7th to the 0th bits are lower byte of the read data. For input of a normal read data, the 17th bit, i.e., the command bit, should be ‘0’.
The multi-port memory device has a serial input/output interface using the above-mentioned protocol (data frame). Since the multi-port memory device has a plurality of ports, plural operations can be performed simultaneously. For instance, while a write operation is performed at the first port PORT0, a read operation can be performed at the second port PORT1. In this manner, a large quantity of data can be processed at high speed. Therefore, the multi-port memory device can be employed in a device which processes a large quantity of audio/video data, e.g., a digital television.
Meanwhile, for testing the multi-port memory device, tests should be performed through the ports (PORT0 to PORT3), which have a high speed serial input/output interface. However, in the case of testing, a DRAM test equipment does not support the high speed serial input/output interface at the ports, or the test method cannot be used when there is an error of an logic element included in the ports.
For overcoming the above-mentioned problem, a new structure should be provided so that the testing can be performed independent of the ports and can be supported by DRAM test equipment.
In addition, since the multi-port memory device has a complicated structure including the plurality of ports and the plurality of bank control units, a defective part cannot be easily detected. Under this condition, it is difficult to find a defection of memory cells which have a highest ratio of defective.